Power transistors are utilized nowadays in a large number of applications. So-called “trench FETs” in particular, i.e. field effect transistors whose structure or so-called “trench gate” is implemented substantially within a trench, and whose channel extends in a vertical direction along that trench gate, are enjoying increasing popularity. Very recently there has been increased use of so-called “field plate” trench FETs which have a field plate disposed vertically, i.e. parallel to the depth of the trench, within the trench and below the gate.
When these field plate trench FETs are switched off, when certain conditions exist they transition into the avalanche breakdown state; in other words, the phenomenon of “avalanche breakdown” occurs in the transistors. This state is usually brought about by a high inductance in the so-called “commutation circuit” of a respective field plate trench FET. In the case of an avalanche breakdown of this kind, the maximum of the electric field existing in the semiconductor, and the site or sites of the breakdown, are respectively located at the lower end of the trench of the field plate trench FET, in regions located alongside the trench of the field plate trench FET.
In the case of an avalanche breakdown within such transistors, the physical proximity of the impact ionization maximum, or the physical proximity of the holes generated in the context of that impact ionization, to the gate oxides or field oxides can result in embedding of the aforesaid charge carriers into the oxides or in damage to the oxides and their surfaces by charge carriers accelerated in the field. Embedding of the charge carriers into the oxides is also referred to as “charge trapping.” When breakdown events frequently recur they can result in a degradation of the reverse voltage of the transistor, and ultimately in failure of the component. Components in which corresponding charge carriers are not generated in the immediate vicinity of the oxides are therefore advantageous for applications in which repeated breakdown events occur.
In the existing art this “charge trapping” is avoided by the use of planar components in which the breakdown takes place in the silicon at the P-N transition, i.e. the transition from the so-called “transistor body” or bulk of the transistor to a lightly doped drift zone, so that the charge carriers in question do not reach the oxides located at the surface. For a given active chip area A, however, these planar components exhibit a higher resistance in the drain-source section (also called “Ron”) as compared with trench FETs. The product of Ron and A in such planar transistors is thus greater than with trench FETs.
A particularly low product of Ron and A is achieved using aforesaid trench MOSFETs having compensation electrodes.